JK Flip Flop - Basic Introduction

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This electronics video tutorial provides a basic introduction into the operation of the JK Flip Flop circuit which uses 2 two-input NAND Gates and 2 three-input NAND Gates. The JK Flip Flop circuit is an extension of the SR latch circuit with two additional NAND gates and a clock input. The invalid condition of the SR latch circuit is no longer an issue with the JK Flip Flop. When both J and K inputs are high with an active clock input, the output toggles back and forth between ON and OFF states.

Transistors - NPN & PNP:


Operational Amplifiers:


LED Flasher Circuit:


RC Phase Shift Oscillator Circuit:


555 Timer - Pulse Generator Circuit:


LED Blinking Circuit Using 555 Timer:


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555 Timer Signal Generators:


Diode Logic Gates:


Transistor Logic Gates:


Logic Gates and Truth Tables:


3 Input Logic Gates:


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SR Latch Circuit - Basic Introduction:


SR Latch Circuit - NAND Gates:


SR Flip Flop Circuit:


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Final Exams and Video Playlists:


Full-Length Videos and Worksheets: